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Lattice Semiconductor
IP Core Generation and Evaluation
The following text describes the evaluation implementation flow for Windows platforms. The flow for Linux and
UNIX platforms is described in the Readme file included with the IP core.
Two example top-level reference source files are provided to support TSMAC top-level synthesis and implementa-
tion.
One top file is for a TSMAC IP core only implementation in isolation. This design is intended only to provide an
accurate indication of the device utilization associated with the TSMAC IP core itself and should not be used as an
actual implementation example.
The other top file is for the Test Application Design, and includes both the TSMAC IP core and additional loop back
test logic. This is the same top used in the functional simulation described in the previous section.
Both top-level files ts_mac_core_only_top.v (core only) and ts_mac_top.v (Application) are provided in
\< project_dir >\ts_mac_eval\< username >\src\rtl\top .
Push-button implementation of both reference designs is supported via the project files, ?
< username >_reference_eval.ldf (Diamond) or .syn (ispLEVER), and < username >_core_only_eval.ldf (Diamond) or
.syn (ispLEVER), located in ?
\< project_dir >\ts_mac_eval\< username >\impl\( synplify or precision ) .
Using Project Files With Synplify in Diamond
1. Choose File > Open > Project .
2. Browse to \< project_dir >\ts_mac_eval\< username >\impl\synplify in the Open Project dialog
box.
3. Select and open < username >_reference_eval.ldf or < username >_core_only_eval.ldf. At this point, all of the
files needed to support top-level synthesis and implementation will be imported to the project.
4. In the Diamond Toolbar, choose Project > Active Strategy >Synplify Pro Settings .
5. Set the Frequency (MHz) to 125 in the Synplify Pro pop-up window and close the window.
6. Select the device top-level entry in the left-hand GUI window.
7. Implement the complete design via the standard Diamond GUI flow.
Using Project Files With Synplify in ispLEVER
1. Choose File > Open Project .
2. Browse to \< project_dir >\ts_mac_eval\< username >\impl\synplify in the Open Project dialog
box.
3. Select and open < username >_reference_eval.syn or < username >_core_only_eval.syn. At this point, all of the
files needed to support top-level synthesis and implementation will be imported to the project.
4. Select the top-level source file in the left-hand GUI window (Sources in Project:). Right-click on the
< synthesis_tool > Synthesize Verilog File entry in the right-hand window (Process for current source:) and
select the Properties tab in the pop-up window.
5. Set the Fmax Frequency to 125 MHz in the Properties pop-up window and close the window.
6. Select the device top-level entry in the left-hand GUI window.
7. Implement the complete design via the standard ispLEVER GUI flow.
IPUG51_03.0, December 2010
45
Tri-Speed Ethernet MAC User’s Guide
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相关PDF资料
TS250-130F-2 POLYSWITCH PTC RESET 0.13A SMD
TS250-130F-B-0.5-2 POLYSWITCH PTC RESET 0.13A SMD
TS250-130F-RB-2 POLYSWITCH PTC RESET 0.13A SMD
TS250-130F-RC-2 POLYSWITCH PTC RESET 0.13A SMD
TS250-130F-RC-B-0.5-2 POLYSWITCH PTC RESET 0.13A SMD
TS600-170F-2 POLYSWITCH PTC RESET 0.17A T/R
TS600-200F-RA-B-0.5-2 POLYSWITCH PTC RESET 0.20A SMD
TS600-400F-2 POLYSWITCH PTC RESET 0.40A SMD
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